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Dr. Hsinho Wu is a design engineer at Intel Corporation’s Programmable Solutions Group (formerly Altera). He presently works on high-speed communication systems of FPGA products. His development and research interests include signal integrity, clock and data recovery, equalizations, device and system modeling, simulation techniques, and software architecture.
What are the optimal methods to achieve 224/212 Gb/s common electrical I/O and Ethernet, the highest speed/data rate per lane electrical input/output and link systems? By way of understanding, we begin by investigating optimal pulse amplitude modulationvs. channel characteristics at 224 Gb/s.
This paper explains the theory, implementation, constraints, and cost of using CTLE, FFE, DFE, and FEC equalization schemes for serial links at and above 112 Gbps.
