Design, Simulation, and Validation Challenges of a Scalable 2000 Amp Core Power Rail
DesignCon 2024 Best Paper Award Winner
Designing a power distribution network (PDN) for a scalable 2000 Amp power supply presents numerous challenges. This paper will address these challenges while demonstrating how to design, simulate, and validate a scalable core power rail with a current of 2000 Amp.
The most common architectures for high-current power rails utilize a 48 VDC input to reduce the current to a more manageable level. This 48 VDC input is then pulse width modulated (PWM) and supplied to multiple parallel unregulated resonant DC-DC converter modules to output the ASIC core supply voltage. Alternatively, the 48 VDC could be stepped down to an intermediate 5 VDC or 12 VDC with multiple parallel unregulated resonant DC-DC converter modules and then go through parallel multi-phase PWM switches to regulate the voltage down to the core voltage. Choosing the appropriate architecture involves various tradeoffs, with the small signal and large signal control loop responses being particularly significant. Current sharing between parallel converters is also a crucial consideration, involving the layout symmetry of the printed circuit board and communication between power modules and a central controller. These tradeoffs are typically addressed through simulation, and the use of cascaded power stages requires additional simulator support that was previously unavailable.
This paper also examines additional layout considerations. For instance, clean voltage sense traces are usually included to convey the operating voltage in close proximity to or even on the ASIC package. However, it is critical through simulation and measurement to verify the noise on the sense lines and determine the significance of any crosstalk with the nearby 2000 Amp switching load.
Further, the methodology for measuring and validating the quality of the output current from a 2000 Amp power supply is complicated and challenging. Loading the power rail to the peak power limit of the ASIC is necessary, but if the ASIC is not yet available then a substitute load stepper device must be devised for early testing of the PCB PDN. Additionally, utilizing the ASIC as a litmus test for an adequate power rail design can be costly. Evaluating the large signal response requires dynamically modulating the power rail with an edge speed representative of the ASIC package limit, typically around 100 MHz or a rise/fall time of about 3 ns. While achieving high-current, high-speed modulation is challenging, it is also essential that the measurement of the dynamic current does not impede the dynamic edge.
The goal is to demonstrate how one can effectively validate a 2000 Amp core power rail design using a substitute 2000 Amp step load device. In the process of doing this, it is also necessary to go through an actual design of a scalable 2000 Amp power delivery PDN complete with parallel converters and multiple control loops to understand the design trade-offs and challenges. Modeling of the converters using the latest in measure-based models, and then simulating with the latest in EDA tools for transient, frequency, EM, DC, and electro-thermal are shown to be invaluable for avoiding costly hardware re-spins and melted devices. The scalable 2000 Amp PDN design can then be used to demonstrate the ultra-high speed testing of a core power rail with a dynamic current step-loader for validating large signal time domain transient behavior.
This paper comprehensively addresses these topics and provides a complete process for designing, simulating, and validating a 2000 Amp core power rail. The process involves utilizing a custom-designed evaluation board with a refrigeration-cooled ultra-high-speed in-socket load that is all designed with the latest in power integrity simulation software.
The paper referenced here received the Best Paper Award at DesignCon 2024. To read the entire DesignCon 2024 paper, download the PDF.
