Signal Integrity

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Crosstalk in PCB and packaging interconnects is arguably one of the most complicated phenomena that may cause signal degradation. Crosstalk effects can be treated statistically as a deterministic jitter with a bounded distribution, but the distribution is usually not known. A direct analysis of a worst-case crosstalk scenario may lead to a system overdesign. Neglecting it in design may cause a system failure that is difficult to find and fix later in a design process. Distortions caused by crosstalk cannot be corrected by signal conditioning techniques at a receiver side. It is very important to understand the sources of crosstalk, how to quantify it and how to mitigate it efficiently, as Yuriy Shlepnev demonstrates in this installation of the "How Interconnects Work" series.

Teledyne LeCroy has announced the extension of their patented CrossSync PHY technology to support the PCI Express 6.0 specification.

Teledyne LeCroy and Alphawave Semi unveil PCI Express 7.0 signal generation, transmission, and measurement at DesignCon, showcasing the culmination of their collaborative efforts with results that push the boundaries of signal transmission and measurement technologies.

Electromagnetic simulation tools will almost always give a result for any problem after pressing the run button. But is the result accurate? A methodology is introduced to establish the best practices for using the Ansys 2D Extractor and HFSS tools that include recommendations for the setup conditions, balancing accuracy, and computation time. With this methodology, an error in the absolute accuracy when solving for some electrical features can be achieved to better than 0.3%.

In this article, Yuriy Shlepnev provides an overview of Simbeor electromagnetic signal integrity software and highlights its new features.

Semiconductor signal conditioning and signal recovery innovations have extended data rates by managing allowable signal-to-noise ratio (SNR) at progressively higher Nyquist frequencies. We have experienced how each successive signaling technology increases the electro-mechanical design resolution needed to address the channel physics while respecting the SNR of the chips. These movements throughout the years have provided a baseline of traditional design goals that lead us to better understand today’s 224 Gbps-PAM4 physical layer requirements.

In this article, Cathy Liu discusses how channel error models and FEC performance analysis have been updated according to industry changes, as well as how different Ethernet coding schemes have been studied and simulated for 800GE and 1.6GE systems with 200 Gbps per lane. Liu investigates concatenated FEC with soft-decision decoding for inner code to protect 200 Gbps optical link and the effect of different FEC options on system SI.

In just two generations, six different technological revolutions have transformed our economy, our careers, and our quality of life, for better or for worse. Eric Bogatin reflects upon industry progress and explores the potential impact of the latest development in technological innovation, generative AI.

DesignCon, the premier high-speed communications and system design conference, returns to its home at the Santa Clara Convention Center in Santa Clara, Calif., with technical paper sessions, tutorials, industry panels, product demos, and exhibits, January 30 to February 1, 2024. Group Event Director Suzanne Deffree reflects on the resources, networking, and innovation that DesignCon 2024 will bring.

In the final installment of his article series "DDR5 Electrical and Timing Measurement Techniques," Randy White explores how following a standard workflow for setting up thresholds and timings to distinguish bursts in DDR5 memory interfaces can make design validation much more efficient, ultimately ensuring compliance with specifications and improving system margin by identifying and resolving any issues, especially those related to either read or write transactions.