Eric Bogatin, Signal Integrity Journal Technical Editor

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Holey Swiss cheese offers a popular metaphor for describing planes with a high density of clearance holes, usually under a BGA escape. The concern of many designers is the impact on the inductance in the power and ground planes due to all those holes. Since the gaps between them is narrow, won’t they constrict the current, dramatically increasing the series resistance and the loop inductance of the planes?

If you want to reduce the near end channel to channel cross talk in a differential pair, is it better to use tightly coupled or loosely coupled differential pairs? Take a moment to write down your answer so you can’t change it as you read this.

Every RF engineer learns about the Smith Chart their first day studying S-parameters. It’s an important tool for RF applications. Not so for SI applications. But there are some valuable insights a Smith Chart can illuminate.  Here’s how to extract those few nuggets.

We all strive to, “Get it right the first time,” in our designs, and focus on skills, techniques and tools to help us achieve this. But we should also pay attention to the skills, techniques and tools to “Get it right the second time.” This is a phrase Dave Graef, CTO and General Manager of Teledyne LeCroy likes to use.

Last week, I had the chance to visit with Dennis King at his EMI Test Lab in Longmont, Colorado. While Dennis has been doing EMI testing for more than 30 years, he set up his independent test lab in 2004. With a GTEM and 3-m anechoic chamber, plus stations for ESD and susceptibility testing, he routinely performs testing for CE Mark and FCC emissions and immunity requirements.

DesignCon is like drinking from a firehose. No where will you find a higher density of SI/PI/EMI experts, all in one place. This year, there are over 100 technical presentations, spread over 14 parallel tracks in seven sessions over two days, plus events in the Chiphead Theater, five panel discussions, eight education tutorials by Keysight and three keynote speeches.

The Spring semester is starting at the University of Colorado, Boulder and the next batch of graduate students are taking my signal integrity course. To encourage students to be on time, I use a carrot and a stick. The carrot is a joke of the day and the stick is a pop quiz that happens as soon as class starts.

You would think that interconnect design for rf applications and high-speed digital applications would be very similar. After all, the upper frequency range of the applications are similar. Here area few examples of how rf engineering is different from high speed digital engineering.

If you missed the chance to attend the first EDI CON (Electronic Design Innovation Conference) in Boston last Aug, you missed the first conference to bring together industry participants across the spectrum of rf, microwave, wireless and high speed digital applications of signal integrity, power integrity and EMI. Rarely are these divergent, yet related fields addressed under one roof.

At the recent 2016 IEEE EMC Symposium in Ottawa, I had the opportunity to talk with two of the worlds’ experts on high frequency electrical characterization of interconnects and gained new insight on best practices for connector modeling and measuring.