Signal Integrity Journal Webinar Series

Title: Fast-Track Chiplet Integration with Streamlined UCIe's Electrical Layer Analysis

Date: March 28, 2024

Time: 8am PT / 11am ET

Sponsored by: Keysight

Presented by: Tim Wang-Lee, PhD, Signal Integrity Application Scientist, Keysight

Abstract:
The massification of high-computational applications, such as Artificial Intelligence (AI), is steering the semiconductor industry from monolithic to chiplet-based design architectures. In this new design philosophy, various chip functions once housed within a single large die are now segregated into modular smaller dies, called chiplets, that can be combined in a larger system. As chiplets offer enhanced scalability, flexibility, and cost-effectiveness, they also present new challenges, particularly in die-to-die (D2D) communication. This presentation delves into the key attributes of electrical specification of the UCIe standard, and how to leverage EDA software to analyze the electrical layer efficiently.

In this webinar you will gain insights into the technical foundations of the UCIe standard, and learn how to modernize your design center using workflow-driven EDA tools that accelerate standard and advanced packaging D2D link analysis.

Presenter Bio:
Chun-ting "Tim" Wang Lee, PhD is a Signal Integrity Application Scientist and a high-speed digital applications product manager in Keysight Technologies. Tim received his Ph.D. in Electrical Engineering from the University of Colorado at Boulder in 2020. His work focuses on understanding the printed circuit board fabrication process and how it impacts the on-board Signal Integrity. Lately, he has been presenting ways to improve simulation and measurement correlation. Tim has garnered much acclaim for his well-crafted presentations and memorable delivery style.

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